ASICSoft Inc H-1B wage filings
Roseville, CA. Last filed in fiscal 2026. Figures cover every filing since fiscal 2020; none in the latest 12 months reach five.
ASICSoft Inc filed 16 wage applications for H-1B and similar visas from fiscal 2020 to fiscal 2026. The median wage it offered was $145,005, 7.5% above the government's prevailing wage for the same jobs. Its most-filed job was Hardware VLSI Design Verification Engineer (4 filings, median $130,000).
- Filings since FY2020
- 16
- Positions covered
- 14
- Certified
- 87.5%
- Job titles
- 11
- Worksite cities
- 10
- Last filed
- FY2026
Offered wage since 2020
ASICSoft Inc made 16 filings across 6 fiscal years since 2020, too few in most years to track the wage year by year. Its busiest full year was fiscal 2024, with 4 filings.
Middle half of offered wagesMedian offered wageMedian prevailing wageFilings per year
Fiscal years run October to September. Fiscal 2026 is still running: these figures cover October 2025 to June 2026.
ASICSoft Inc by fiscal year
| Fiscal year | Filings | Median offered | vs year before | Median prevailing | vs prevailing |
|---|---|---|---|---|---|
| 2026 (Oct to Jun) | 2 | n/a | n/a | n/a | n/a |
| 2025 | 3 | n/a | n/a | n/a | n/a |
| 2024 | 4 | $155,000 | n/a | $131,768 | +24.2% |
| 2023 | 2 | n/a | n/a | n/a | n/a |
| 2022 | 0 | n/a | n/a | n/a | n/a |
| 2021 | 2 | n/a | n/a | n/a | n/a |
| 2020 | 3 | $130,000 | n/a | $126,090 | +6.7% |
Offered wage by job title
Middle half of offered wagesMedian offered wageMedian prevailing wage
| Job title | Filings | Median offered | Offered range and prevailing wage | vs prevailing |
|---|---|---|---|---|
| Hardware VLSI Design Verification Engineer | 4 | $130,000 | +3.1% | |
| Senior Hardware VLSI ASIC Design Verification Engineer | 2 | $145,005 | +6.9% | |
| VLSI Design Verification Engineer | 2 | $203,840 | +0.3% | |
| 5G O-RAN Test Engineer | 1 | $101,920 | +15.3% | |
| ASIC Verification Engineer | 1 | $187,200 | +8.3% | |
| ASICSoft, Inc. | 1 | n/a | ||
| Embedded Systems Engineer | 1 | $130,000 | +19.4% | |
| Hardware ASIC Verification Engineer | 1 | $156,000 | +6.7% | |
| Hardware Design Engineer | 1 | $155,000 | +17.6% | |
| Hardware VLSI ASIC Design Verification Engineer | 1 | $103,106 | at the minimum | |
| Senior Member Technical Staff, Design Verification | 1 | $228,800 | +51.9% | |
No job title on this page matches. Only the most-filed titles are listed.
Where the jobs are
| Worksite | Filings | Median offered |
|---|---|---|
| Roseville, CA | 3 | $130,000 |
| Apex, NC | 2 | $208,000 |
| Frisco, TX | 2 | $117,978 |
| Milpitas, CA | 2 | $155,000 |
| Sunnyvale, CA | 2 | $203,840 |
| Littleton, CO | 1 | $101,920 |
| Menlo Park, CA | 1 | $156,000 |
| Pleasanton, CA | 1 | $103,106 |
| Raleigh, NC | 1 | $140,000 |
| Wilmington, MA | 1 | $150,010 |
By visa type: 16 H-1B. By outcome: 14 certified, 2 withdrawn before a decision.
Seniority of the jobs filed
The government assigns each job one of four wage levels. A higher level means a higher legal minimum.
What these numbers are
- They are wages ASICSoft Inc attested to on Labor Condition Applications (Form ETA-9035), not paychecks. Bonuses and stock are not included.
- A filing is not a visa or a hire. One filing can cover several positions, and some are later withdrawn. Wage figures use certified filings only.
- The prevailing wage is the minimum the employer must pay for that job in that area, set from government wage surveys.
Source: U.S. Department of Labor, OFLC disclosure data. How we clean and count it.
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